1. Field of the invention
The present invention relates to a memory controller configured to perform control for storing and reading data from a host into and out from a NAND-type flash memory section having a plurality of memory cells, a semiconductor memory device which includes the memory controller, and a control method of the semiconductor memory device.
2. Description of the Related Art
Nonvolatile semiconductor memory devices having a NAND-type flash memory section performs processing to erase data stored in a plurality of memory cells called a block at once, so that a structure of the memory device is simplified and low cost and high capacity are achieved. Further, since semiconductor memory devices have no moving section and their power consumption is low, they have been widely used as storage devices of hosts of portable telephones, portable music players or the like. However, the NAND-type flash memory section has a limit on the number of writes/erasures and the number of readouts.
As for write/erase processing with respect to a memory cell of the NAND-type flash memory section, a limit on the number of writes/erasures is caused because high voltage is applied to a gate on a substrate and an electron is injected into a floating gate. If write/erase processing is executed many times, an oxide film around the floating gate is degraded and data may be destroyed. To prevent write/erase processing from concentrating on a certain memory cell, so-called wear leveling is performed in which a memory controller counts the number of erase processes, replaces a memory cell whose number of erase processing is large with a memory cell whose number of erase processing is small so that the numbers of write/erase processing are averaged.
In a semiconductor memory device which performs the wear leveling, it is difficult for a host to identify a data storage position using a physical address which indicates a physical position of a memory cell in a memory section. To solve this, a concept of logical space is constructed and a physical address is converted to a logical address which indicates a position of a memory cell in the logical space. A logical-physical address conversion table (hereinafter referred to as a “conversion table”) is used to convert a logical address to physical address.
On the other hand, the limit on the number of readouts is caused by read disturb. In a case of the NAND-type flash memory section, the read disturb refers to a phenomenon in which electrons are injected gradually into a floating gate because read voltage is applied also to non-selected memory cell from a word line. Therefore, as only readout processing is repeated for readout from a memory cell which stores data, threshold voltage during data readout is changed, that is, a data storage condition is degraded. Accordingly, readout errors are increased, and reliability of read-out data is decreased.
For example, Japanese Patent Application Laid-Open Publication No. 2004-326867 has disclosed that in order to prevent read disturb, rewrite processing is performed on a memory cell whose number of readouts is large as necessary, that is, refresh processing is performed to return threshold voltage in its original state.
In refresh processing in known semiconductor memory devices, a memory cell is identified using a physical address, and thereby the number of readouts is counted and managed. However, since the number of readouts is counted while a logical address is associated with a physical address with respect to memory cells in all area divided into block units, processing is complicated. Furthermore, since a storage section associated with a conversion table in a complicated manner is required, a circuit size is increased.
On the other hand, tolerances of read disturb of a plurality of memory cells in a memory section are very different depending on factors such as manufacturing variations and position in the memory section. To ensure reliability of data to be read out in spite of read disturb, refresh processing needs to be performed at every predetermined number of readings, in which harmful effect does not occur even in a reference memory cell where read disturb is most likely to occur among the plurality of memory cells. However, excessive refresh processing leads to an increase of the number of writes/erasures more than necessary so that the memory cells are degraded, and the reliability of data to be read out may be reduced on the contrary.